Interface Synthesis for FPGA Based VLSI Processor Arrays

FPGA based VLSI processor arrays provide an enormous computation performance along with the flexibility of reconfigurable logic. In the future, hybrid processors will become available that consist of a RISC core and configurable logic area on the same die. This allows for the efficient usage of a VLSI array as a coprocessor to the RISC core. Due to their high performance, VLSI array structures require interfaces with a large bandwidth, even under hard resource constraints as given in embedded systems. In this work, we present a generic interface hardware model that can be easily adapted to various performance and resource constraints.